In this role you will be familiar with cutting edge power management techniques including power management ICs control schemes, Chip power state transitions, SoC boot process and HW security solutions. You will define uArch spec, implement HW including RTL and UPF coding, synthesize the digital design to the latest process nodes and participate in the implementation process. Your responsibilities in this role likely to include: Micro-architecture definitions at the unit level RTL coding, block level simulations and synthesis Work closely with verification team on block/top level to ensure timely delivery of quality designs Work closely with physical design team to optimize the design and to meet the targets set for a certain unit (area, timing, and power)


Key Qualifications
  • BS/MS in EE/CE
  • 3+ years of experience in digital design (preferably in SoC)
  • Familiar with advanced design practices (clock/voltage domain crossing, low power design and DFT) – Advantage
  • Familiar with various chip development tools (e.g. lint, synthesis, STA)
  • Familiar with verification methodologies
  • Strong Verilog/System Verilog skills
  • Experienced with scripting using common languages (e.g. Python, Perl, TCL)

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