Education & Experience
  • B.Sc / M.Sc Electric Engineering / Computer Engineering
  • As a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.
  • Implementation – Block level PnR, floor-planning, clock, power planning and distribution.
  • Verification and Analysis – Static Timing closure using commercial tools, Physical Verification as well as Electrical/Power Analysis (EM / IR-Drop / Xtalk / noise )

Key Qualifications

  • 5+ years of experience in physical design of large scale SoCs.
  • Extensive experience with one of the place & route tools (Synopsys / Cadence).
  • Familiar with hierarchical design approach, top-down design, timing and physical convergence.
  • In-depth understanding of static-timing analysis, experience with STA sign-off tools.
  • Extensive know-how in clock/power distribution and analysis, RC extraction and PnR/signoff correlation.
  • Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
  • Scripting and Programming experience using either TCL or Python or Perl or known Shell scripting languages.
  • Knowledge in Verilog – advantage.

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